IS61S32IS61S32K x 32 SYNCHRONOUSPIPELINE STATIC RAMDESCRIPTION
The ICSI IS61S32 is a high-speed, low-powersynchronous static RAM designed to provide a burstable,high-performance, secondary cache for the Pentium™,680X0™, and PowerPC™ microprocessors. It is organizedas 65,536 words by 32 bits, fabricated with ICSI's advancedCMOS technology. The device integrates a 2-bit burstcounter, high-speed SRAM core, and high-drive capabilityoutputs into a single monolithic circuit. All synchronousinputs pass through registers controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by therising edge of the clock input. Write cycles can be from oneto four bytes wide as controlled by the write control inputs.Separate byte enables allow individual bytes to be written.BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3controls DQ17-DQ24, BW4 controls DQ25-DQ32,conditioned by BWE being LOW. A LOW on GW input wouldcause all bytes to be written.
Bursts can be initiated with either ADSP (Address StatusProcessor) or ADSC (Address Status Cache Controller)input pins. Subsequent burst addresses can be generatedinternally by the IS61S32 and controlled by the ADV (burstaddress advance) input pin.
Asynchronous signals include output enable (OE), sleepmode input (ZZ), clock (CLK) and burst mode input (MODE).A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), theSRAM normally operates after three cycles of the wake-upperiod. A LOW input, i.e., GNDQ, on MODE pin selectsLINEAR Burst. A VCCQ (or no connect) on MODE pin selectsINTERLEAVED Burst.
FEATURES
•Internal self-timed write cycle
•Individual Byte Write Control and Global Write•Clock controlled, registered address, data andcontrol
•Pentium™ or linear burst sequence control usingMODE input
•Three chip enables for simple depth expansionand address pipelining
•Common data inputs and data outputs•Power-down control by ZZ input
•JEDEC 100-Pin LQFP and PQFP package•Single +3.3V power supply
•Two Clock enables and one Clock disable toeliminate multiple bank bus contention•Control pins mode upon power-up:– MODE in interleave burst mode– ZZ in normal operation mode
These control pins can be connected to GNDQor VCCQ to alter their power-up state•Industrial temperature available
FAST ACCESS TIME
SymboltKQtKC —ParameterCLK Access TimeCycle TimeFrequency-200(1)45200-16656166-13357.5133-11758.5117-5510100-661283-771375-881566UnitnsnsMHzNote:1.ADVANCE INFORMATION ONLY.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errorswhich may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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IS61S32
BLOCK DIAGRAM
MODECLKCLKQ0A0A0’BINARYCOUNTERADVADSCADSPCECLRQ1A1A1’K x 32MEMORYARRAY1416A15-A016DQADDRESSREGISTERCECLK3232GWBWEBW4DQDQ32-DQ25BYTE WRITEREGISTERSCLKDBW3QDQ24-DQ17BYTE WRITEREGISTERSCLKDBW2QDQ16-DQ9BYTE WRITEREGISTERSCLKDBW1QDQ8-DQ1BYTE WRITEREGISTERSCLKCE1CE2CE3DQ4ENABLEREGISTERCECLKINPUTREGISTERSCLKOUTPUTREGISTERSCLKOE32DATA[32:1]DQENABLEDELAYREGISTERCLKOE2Integrated Circuit Solution Inc.
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IS61S32
PIN CONFIGURATION
100-Pin LQFP and PQFP (Top View)
A6A7CE1CE2BW4BW3BW2BW1CE3VCCGNDCLKGWBWEOEADSCADSPADVA8A91009997969594939291908887868584838281NCDQ17DQ18VCCQGNDQDQ19DQ20DQ21DQ22GNDQVCCQDQ23DQ24VCCQVCCNCGNDDQ25DQ26VCCQGNDQDQ27DQ28DQ29DQ30GNDQVCCQDQ31DQ32NC123456710111213141516171819202122232425262728293031323334353637383940414243444547484950MODEA5A4A3A2A1A0NCNCGNDVCCNCNCA10A11A12A13A14A15NC8079787776757473727170696867666563626160595857565554535251NCDQ16DQ15VCCQGNDQDQ14DQ13DQ12DQ11GNDQVCCQDQ10DQ9GNDNCVCCZZDQ8DQ7VCCQGNDQDQ6DQ5DQ4DQ3GNDQVCCQDQ2DQ1NCPIN DESCRIPTIONS
A0-A15CLKADSPADSCADVBW1-BW4BWEGW
CE1, CE2, CE3
Address InputsClock
Processor Address StatusController Address StatusBurst Address AdvanceSynchronous Byte Write EnableByte Write EnableGlobal Write EnableSynchronous Chip Enable
OEDQ1-DQ32ZZMODEVCCGNDVCCQGNDQNC
Output EnableData Input/OutputSleep Mode
Burst Sequence Mode+3.3V Power SupplyGround
Isolated Output Buffer Supply: +3.3VIsolated Output Buffer GroundNo Connect
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IS61S32
TRUTH TABLE
Operation
Deselected, Power-downDeselected, Power-downDeselected, Power-downDeselected, Power-downDeselected, Power-downRead Cycle, Begin BurstRead Cycle, Begin BurstWrite Cycle, Begin BurstRead Cycle, Begin BurstRead Cycle, Begin BurstRead Cycle, Continue BurstRead Cycle, Continue BurstRead Cycle, Continue BurstRead Cycle, Continue BurstWrite Cycle, Continue BurstWrite Cycle, Continue BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstWrite Cycle, Suspend BurstWrite Cycle, Suspend Burst
AddressUsedNoneNoneNoneNoneNone External External External External ExternalNextNextNextNextNextNext Current Current Current Current Current Current
CE1HLLLLLLLLL X X H H X H X X H H X H
CE2XLXLXHHHHHXXXXXXXXXXXX
CE3XXHXHLLLLLXXXXXXXXXXXX
ADSPADSCXLLHHLLHHHHHXXHXHHXXHX
LXXLLXXLLLHHHHHHHHHHHH
ADVWRITEXXXXXXXXXXLLLLL LHHHHHH
XXXXXXXLHHHHHHLLHHHHLL
OEXXXXXLHXLHLHLHXXLHLHXX
DQHigh-ZHigh-ZHigh-ZHigh-ZHigh-ZQHigh-ZDQHigh-ZQHigh-ZQHigh-ZDDQHigh-ZQHigh-ZDD
Notes:
1.All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).2.Wait states are inserted by suspending burst.
3.\"X\" means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW isLOW. WRITE=H means all byte write enable signals are HIGH.
4.For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and heldHIGH throughout the input data hold time.
5.ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one ormore byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
FunctionREADREAD
WRITE Byte 1WRITE All BytesWRITE All Bytes
GWHHHXL
BWEHXLLX
BW1XHLLX
BW2XHHLX
BW3BW4XHHLX
XHHLX
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IS61S32
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address
A1A0
00011011
1st Burst Address
A1A0
01001110
2nd Burst Address
A1A0
10110001
3rd Burst Address
A1A0
11100100
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0A1’, A0’ = 1,10,11,0ABSOLUTE MAXIMUM RATINGS(1,2,3)
SymbolTBIASTSTGPDIOUT
VIN, VOUTVIN
Parameter
Temperature Under BiasStorage TemperaturePower Dissipation
Output Current (per I/O)
Voltage Relative to GND for I/O Pins
Voltage Relative to GND for for Address and Control Inputs
Value–10 to +85–55 to +150
1.8100
–0.5 to VCCQ + 0.3
–0.5 to 5.5
Unit°C°CWmAVV
Notes:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This isa stress rating only and functional operation of the device at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affectreliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however,precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE
Range
CommercialIndustrial
Ambient Temperature
0°C to +70°C–40°C to +85°C
VCC
3.3V +10%, –5%3.3V +10%, –5%
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IS61S32
DC ELECTRICAL CHARACTERISTICS(1,2) (Over Operating Range)
SymbolVOHVOLVIHVILILIILO
Parameter
Output HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW VoltageInput Leakage CurrentOutput Leakage Current
GND ≤ VIN ≤ VCCQ(2)
GND ≤ VOUT ≤ VCCQ, OE = VIH
Com.Ind.Com.Ind.
Test ConditionsIOH = –5.0 mAIOL = 5.0 mA
Min.2.4—2.0–0.3–5–10–5–10
Max.—0.4VCCQ + 0.3
0.8510510
UnitVVVVµAµA
Notes:
1.MODE pin have an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect,tied to GND,or tied to VCCQ.
2.MODE pin should be tied to Vcc or GND. They exhibit ±30 µA maximum leakage current when tiedto ≤ GND + 0.2V or ≥ Vcc – 0.2V.
POWER SUPPLY CHARACTERISTICS (Operating Range)
SymbolParameterICCAC OperatingSupply CurrentTest ConditionsDevice Selected,Com.All Inputs = VIL or VIHInd.OE = VIH, Cycle Time ≥ tKC min.Com.Ind.Com.Ind.-200(1)Min.Max.——————400—100—5—-166Min.Max.——————215—70—5—-133Min.Max.——————205—60—5—-117Min.Max.Unit——————1952055060510mAISBStandby CurrentDevice Deselected,VCC = Max.,CLK Cycle Time ≥ tKC min.Power-DownMode CurrentZZ = VCCQ, CLK RunningAll Inputs ≤ GND + 0.2V or ≥ VCC – 0.2VmAIZZmANote:1.ADVANCE INFORMATION ONLY.
SymbolParameterICCAC OperatingSupply CurrentTest ConditionsDevice Selected,Com.All Inputs = VIL or VIHInd.OE = VIH, Cycle Time ≥ tKC min.Com.Ind.Com.Ind.-5Min.Max.——————1751852535510-6Min.Max.——————1651752535510-7Min.Max.——————1501602535510-8Min.Max.Unit——————1401502535510mAISBStandby CurrentDevice Deselected,VCC = Max.,CLK Cycle Time ≥ tKC min.Power-DownMode CurrentZZ = VCCQ, CLK RunningAll Inputs ≤ GND + 0.2V or ≥ VCC – 0.2VmAIZZmA6Integrated Circuit Solution Inc.
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IS61S32
CAPACITANCE(1,2)
SymbolCINCOUT
ParameterInput CapacitanceInput/Output Capacitance
ConditionsVIN = 0VVOUT = 0V
Max.68
UnitpFpF
Notes:
1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall TimesInput and Output Timingand Reference LevelOutput Load
Unit0V to 3.0V1.5 ns1.5VSee Figures 1 and 2
AC TEST LOADS
317 Ω ZO = 50ΩOutputBuffer50Ω3.3VOUTPUT30 pF1.5V5 pFIncludingjig andscope351 ΩFigure 1
Figure 2
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IS61S32
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
SymboltKCtKHtKLtKQtKQX(2)tKQLZ(2,3)tKQHZ(2,3)tOEQtOEQX(2)tOELZ(2,3)tOEHZ(2,3)tAStSStWStCEStAVStAHtSHtWHtCEHtAVHtCFG(4)ParameterCycle TimeClock High TimeClock Low TimeClock Access TimeClock High to Output InvalidClock High to Output Low-ZClock High to Output High-ZOutput Enable to Output ValidOutput Disable to Output InvalidOutput Enable to Output Low-ZOutput Disable to Output High-ZAddress Setup TimeAddress Status Setup TimeWrite Setup TimeChip Enable Setup TimeAddress Advance Setup TimeAddress Hold TimeAddress Status Hold TimeWrite Hold TimeChip Enable Hold TimeAddress Advance Hold TimeConfiguration Setup-200(1)Min.Max.51.61.6—101—00—222220.50.50.50.50.525———4——3.53.5——3———————————-166Min.Max.62.42.4—1.501.5—00—2.52.52.52.52.50.50.50.50.50.525———5——55——3———————————-133Min.Max.7.52.82.8—1.501.5—00—2.52.52.52.52.50.50.50.50.50.530———5——55——3———————————-117Min.Max8.533—1.501.5—00—2.52.52.52.52.50.50.50.50.50.535———5——65——4———————————UnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsNotes:1.ADVANCE INFORMATION ONLY.
2.Guaranteed but not 100% tested. This parameter is periodically sampled.3.Tested with load in Figure 2.
4.Configuration signal MODE is static and must not change during normal operation.
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IS61S32
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) (Continued)
-5SymboltKCtKHtKLtKQtKQX(1)tKQLZ(1,2)tKQHZ(1,2)tOEQtOEQX(1)tOELZ(1,2)tOEHZ(1,2)tAStSStWStCEStAVStAHtSHtWHtCEHtAVHtCFG(3)ParameterCycle TimeClock High TimeClock Low TimeClock Access TimeClock High to Output InvalidClock High to Output Low-ZClock High to Output High-ZOutput Enable to Output ValidOutput Disable to Output InvalidOutput Enable to Output Low-ZOutput Disable to Output High-ZAddress Setup TimeAddress Status Setup TimeWrite Setup TimeChip Enable Setup TimeAddress Advance Setup TimeAddress Hold TimeAddress Status Hold TimeWrite Hold TimeChip Enable Hold TimeAddress Advance Hold TimeConfiguration SetupMin.103.53.5—1.501.5—00—2.52.52.52.52.50.50.50.50.50.535Max.———5——65——4———————————Min.1244—1.501.5—00—2.52.52.52.52.50.50.50.50.50.545-6Max.———6——66——5———————————Min.1366—202—00—2.52.52.52.52.50.50.50.50.50.566.7-7Max.———7——66——6———————————Min.1566—202—00—2.52.52.52.52.50.50.50.50.50.580-8Max———8——66——6———————————UnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsNotes:
1.Guaranteed but not 100% tested. This parameter is periodically sampled.2.Tested with load in Figure 2.
3.Configuration signal MODE is static and must not change during normal operation.
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IS61S32
READ CYCLE TIMING: PIPELINE
tKCCLKtSStSHtKHtKLADSP is blocked by CE1 inactiveADSC initiate readtAVHADSPtSStSHADSCtAVSSuspend BurstADVtAStAHA15-A0RD1tWStWHRD2RD3GWtWStWHBWEBW4-BW1tCEStCEHCE1 Masks ADSPCE1tCEStCEHCE2 and CE3 only sampled with ADSP or ADSCUnselected with CE2CE2tCEStCEHCE3tOEQtOEHZOEtOELZtOEQXtKQXDATAOUTHigh-ZtKQLZtKQ1a2a2b2c2d3atKQHZDATAINHigh-ZPipelined ReadSingle ReadBurst ReadUnselected10Integrated Circuit Solution Inc.
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IS61S32
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
SymboltKCtKHtKLtAStSStWStDStCEStAVStAHtSHtDHtWHtCEHtAVHtCFG(2)ParameterCycle TimeClock High TimeClock Low TimeAddress Setup TimeAddress Status Setup TimeWrite Setup TimeData In Setup TimeChip Enable Setup TimeAddress Advance Setup TimeAddress Hold TimeAddress Status Hold TimeData In Hold TimeWrite Hold TimeChip Enable Hold TimeAddress Advance Hold TimeConfiguration Setup-200(1)Min.Max.51.61.62222220.50.50.50.50.50.525————————————————-166Min.Max.62.42.42.52.52.52.52.52.50.50.50.50.50.50.525————————————————-133-117Min.Max.Min.Max.7.52.82.82.52.52.52.52.52.50.50.50.50.50.50.530————————————————8.5332.52.52.52.52.52.50.50.50.50.50.50.535————————————————UnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsSymboltKCtKHtKLtAStSStWStDStCEStAVStAHtSHtDHtWHtCEHtAVHtCFG(2)
ParameterCycle TimeClock High TimeClock Low TimeAddress Setup TimeAddress Status Setup TimeWrite Setup TimeData In Setup TimeChip Enable Setup TimeAddress Advance Setup TimeAddress Hold TimeAddress Status Hold TimeData In Hold TimeWrite Hold TimeChip Enable Hold TimeAddress Advance Hold TimeConfiguration Setup
-5
Min.Max.103.53.52.52.52.52.52.52.50.50.50.50.50.50.535
————————————————
-6
Min.Max.12442.52.52.52.52.52.50.50.50.50.50.50.545
————————————————
-7-8
Min.Max.Min.Max.13662.52.52.52.52.52.50.50.50.50.50.50.552
————————————————
15662.52.52.52.52.52.50.50.50.50.50.50.560
————————————————
Unitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
Note:
1.ADVANCE INFORMATION ONLY.
2. Configuration signal MODE is static and must not change during normal operation.
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IS61S32
WRITE CYCLE TIMING
tKCCLKtSStSHtKHtKLADSP is blocked by CE1 inactiveADSC initiate WriteADSPADSCADV must be inactive for ADSP WritetAVSADVtAStAHtAVHA15-A0WR1tWStWHWR2WR3GWtWStWHBWEtWStWHtWStWHBW4-BW1tCEStCEHWR1WR2CE1 Masks ADSPWR3CE1tCEStCEHCE2 and CE3 only sampled with ADSP or ADSCUnselected with CE2CE2tCEStCEHCE3OEHigh-ZtDStDHDATAOUTDATAINHigh-Z1aBW4-BW1 only are applied to first cycle of WR22a2b2c2d3aSingle WriteBurst WriteWriteUnselected12Integrated Circuit Solution Inc.
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IS61S32
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
SymboltKCtKHtKLtKQtKQX(2)tKQLZ(2,3)tKQHZ(2,3)tOEQtOEQX(2)tOELZ(2,3)tOEHZ(2,3)tAStSStWStCEStAHtSHtWHtCEHtCFG(4)ParameterCycle TimeClock High TimeClock Low TimeClock Access TimeClock High to Output InvalidClock High to Output Low-ZClock High to Output High-ZOutput Enable to Output ValidOutput Disable to Output InvalidOutput Enable to Output Low-ZOutput Disable to Output High-ZAddress Setup TimeAddress Status Setup TimeWrite Setup TimeChip Enable Setup TimeAddress Hold TimeAddress Status Hold TimeWrite Hold TimeChip Enable Hold TimeConfiguration Setup1—00—22220.50.50.50.525-200(1)Min.Max.51.61.6—1———4——3.53.5——3—————————-166Min.Max.62.42.4—1.501.5—00—2.52.52.52.50.50.50.50.525———5——55——3—————————-133-117Min.Max.Min.Max.7.52.82.8—1.501.5—00—2.52.52.52.50.50.50.50.530———5——55——3—————————8.533—1.501.5—00—2.52.52.52.50.50.50.50.535———5——65——4—————————UnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsNotes:1.ADVANCE INFORMATION ONLY.
2.Guaranteed but not 100% tested. This parameter is periodically sampled.3.Tested with load in Figure 2.
4.Configuration signal MODE is static and must not change during normal operation.
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IS61S32
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) (Continued)
SymboltKCtKHtKLtKQtKQX(1)tKQLZ(1,2)tKQHZ(1,2)tOEQtOEQX(1)tOELZ(1,2)tOEHZ(1,2)tAStSStWStCEStAHtSHtWHtCEHtCFG(3)
ParameterCycle TimeClock High TimeClock Low TimeClock Access TimeClock High to Output InvalidClock High to Output Low-ZClock High to Output High-ZOutput Enable to Output ValidOutput Disable to Output InvalidOutput Enable to Output Low-ZOutput Disable to Output High-ZAddress Setup TimeAddress Status Setup TimeWrite Setup TimeChip Enable Setup TimeAddress Hold TimeAddress Status Hold TimeWrite Hold TimeChip Enable Hold TimeConfiguration Setup
-5
Min.Max.103.53.5—1.501.5—00—2.52.52.52.50.50.50.50.535
———5——65——4—————————
-6
Min.Max.1244—1.501.5—00—2.52.52.52.50.50.50.50.545
———6——66——5—————————
-7-8
Min.Max.Min.Max.1366—202—00—2.52.52.52.50.50.50.50.552
———7——66——6—————————
1566—202—00—2.52.52.52.50.50.50.50.560
———8——66——6—————————
Unitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
Notes:
1.Guaranteed but not 100% tested. This parameter is periodically sampled.2.Tested with load in Figure 2.
3.Configuration signal MODE is static and must not change during normal operation.
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IS61S32
READ/WRITE CYCLE TIMING: PIPELINE
tKCCLKtSStSHtKHtKLADSP is blocked by CE1 inactiveADSPtSStSHADSCADVtAStAHA15-A0RD1tWStWHWR1RD2RD3GWtWStWHBWEtWStWHBW4-BW1tCEStCEHWR1CE1 Masks ADSPCE1tCEStCEHCE2 and CE3 only sampled with ADSP or ADSCCE2tCEStCEHUnselected with CE3CE3tOEQtOEHZOEtOELZtOEQXtKQXDATAOUTHigh-ZtKQLZtKQ1atKQXtKQHZ2a2b2c2dtKQHZDATAINHigh-ZtDS1atDHSingle ReadSingle WriteBurst ReadUnselectedIntegrated Circuit Solution Inc.
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IS61S32
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS(1) (Over OperatingRange)SymboltKCtKHtKLtKQtKQX(3)tKQLZ(3,4)tKQHZ(3,4)tOEQtOEQX(3)tOELZ(3,4)tOEHZ(3,4)tAStSStCEStAHtSHtCEHtZZS(5)tZZREC(6)ParameterCycle TimeClock High TimeClock Low TimeClock Access TimeClock High to Output InvalidClock High to Output Low-ZClock High to Output High-ZOutput Enable to Output ValidOutput Disable to Output InvalidOutput Enable to Output Low-ZOutput Disable to Output High-ZAddress Setup TimeAddress Status Setup TimeChip Enable Setup TimeAddress Hold TimeAddress Status Hold TimeChip Enable Hold TimeZZ StandbyZZ Recovery-200(2)Min.Max.51.61.6—101—00—222222—8———4——3.53.5——3——————8—-166Min.Max62.42.4—1.501.5—00—2.52.52.52.52.52.522———5——55——3————————-133-117Min.Max.Min.Max.7.52.82.8—1.501.5—00—2.52.52.52.52.52.522———5——55——3————————8.533—1.501.5—00—2.52.52.52.52.52.522———5——65——4————————UnitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnscyccycNotes:
1.Configuration signal MODE is static and must not change during normal operation.2.ADVANCE INFORMATION ONLY.
3.Guaranteed but not 100% tested. This parameter is periodically sampled.4.Tested with load in Figure 2.
5.The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Dataretention is guaranteed when ZZ is asserted and clock remains active.
6.ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state.
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IS61S32
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS(1) (Over OperatingRange) (Continued)SymboltKCtKHtKLtKQtKQX(2)tKQLZ(2,3)tKQHZ(2,3)tOEQtOEQX(2)tOELZ(2,3)tOEHZ(2,3)tAStSStCEStAHtSHtCEHtZZS(4)tZZREC(5)
ParameterCycle TimeClock High TimeClock Low TimeClock Access TimeClock High to Output InvalidClock High to Output Low-ZClock High to Output High-ZOutput Enable to Output ValidOutput Disable to Output InvalidOutput Enable to Output Low-ZOutput Disable to Output High-ZAddress Setup TimeAddress Status Setup TimeChip Enable Setup TimeAddress Hold TimeAddress Status Hold TimeChip Enable Hold TimeZZ StandbyZZ Recovery
-5
Min.Max.103.53.5—1.501.5—00—2.52.52.52.52.52.522
———5——65——4————————
-6
Min.Max.1244—1.501.5—00—2.52.52.52.52.52.522
———6——66——5————————
-7-8
Min.Max.Min.Max.1366—202—00—2.52.52.52.52.52.522
———7——66——6————————
1566—202—00—2.52.52.52.52.52.522
———8——66——6————————
Unitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnscyccyc
Notes:
1.Configuration signal MODE is static and must not change during normal operation.2.Guaranteed but not 100% tested. This parameter is periodically sampled.3.Tested with load in Figure 2.
4.The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Dataretention is guaranteed when ZZ is asserted and clock remains active.
5.ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state.
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IS61S32
SNOOZE AND RECOVERY CYCLE TIMING
tKCCLKtSStSHtKHtKLADSPADSCADVtAStAHA15-A0RD1RD2GWBWEBW4-BW1tCEStCEHCE1tCEStCEHCE2tCEStCEHCE3tOEQtOEHZOEtOELZtOEQXDATAOUTHigh-ZtKQLZtKQ1atKQXtKQHZDATAINHigh-ZtZZStZZRECZZSingle ReadSnooze with Data RetentionRead18Integrated Circuit Solution Inc.
SSE003-0B
元器件交易网www.cecb2b.com
IS61S32
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency (MHz)Order Part Number
200166133117100837566
Package
IS61S32-200TQ14*20*1.4mm LQFPIS61S32-200PQ14*20*2.7mm PQFPIS61S32-166TQ14*20*1.4mm LQFPIS61S32-166PQ14*20*2.7mm PQFPIS61S32-133TQ14*20*1.4mm LQFPIS61S32-133PQ14*20*2.7mm PQFPIS61S32-117TQ14*20*1.4mm LQFPIS61S32-117PQ14*20*2.7mm PQFPIS61S32-5TQIS61S32-5PQIS61S32-6TQIS61S32-6PQIS61S32-7TQIS61S32-7PQIS61S32-8TQIS61S32-8PQ
14*20*1.4mm LQFP14*20*2.7mm PQFP14*20*1.4mm LQFP14*20*2.7mm PQFP14*20*1.4mm LQFP14*20*2.7mm PQFP14*20*1.4mm LQFP14*20*2.7mm PQFP
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Frequency (MHz)
117100837566
Order Part Number
Package
IS61S32-117TQI14*20*1.4mm LQFPIS61S32-117PQI14*20*2.7mm PQFPIS61S32-5TQIIS61S32-5PQIIS61S32-6TQIIS61S32-6PQIIS61S32-7TQIIS61S32-7PQIIS61S32-8TQIIS61S32-8PQI
14*20*1.4mm LQFP14*20*2.7mm PQFP14*20*1.4mm LQFP14*20*2.7mm PQFP14*20*1.4mm LQFP14*20*2.7mm PQFP14*20*1.4mm LQFP14*20*2.7mm PQFP
Integrated Circuit Solution Inc.
SSE003-0B
19
元器件交易网www.cecb2b.com
IS61S32
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140FAX: 886-2-26962252http://www.icsi.com.tw
20
Integrated Circuit Solution Inc.
SSE003-0B
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